Semiconductor memory devices include a bit line sense amplifier circuit in order to sense and amplify data stored in a memory cell. The typical sensing method of a bit line sense amplifier is called differential pair sensing, and the most universally used sense amplifier is a cross-coupled latch sense amplifier, in which invalid sensing, that is, sensing of invalid data, may be caused by a mismatch, for example, mismatch in threshold voltage, between circuit elements, for example, transistors.
The structures of the bit lines in semiconductor memory devices may be divided into a folded structure and an open structure. FIG. 1 is a schematic diagram illustrating a conventional folded bit line structure and FIG. 2 is a schematic diagram illustrating a conventional open bit line structure.
Referring to FIG. 1, in a semiconductor memory device using the folded bit line structure, a sense amplifier (S/A) block 110 may be shared by two memory cell blocks 100L and 100R. Memory cells can not be formed at every intersection of the word lines WL and pairs of bit lines BL_L and /BL_L and BL_R and /BL_R. Accordingly, the size of a memory cell array with a folded structure is greater than that in the open bit line structure. When sensing and amplifying memory cell data in the memory cell block 100L, the S/A block 110 is connected with the pair of the bit lines BL_L and /BL_L crossing the memory cell block 100L and senses and amplifies signals of the pair of the bit lines BL_L and /BL_L using the differential pair sensing. At this time, one of the two bit lines BL_L and /BL_L is loaded with a voltage corresponding to the memory cell data and the other bit line acts as a reference voltage line.
Referring to FIG. 2, in a semiconductor memory device using the open bit line structure, an S/A block 210 may also be shared by two memory cell blocks 200L and 200R. Memory cells can be formed at every intersection of the word lines WL and the bit lines BL_L and BL_R. Accordingly, as illustrated in FIG. 2, the size of a memory cell array having the open bit line structure can be reduced, as compared to that using the folded bit line structure. When sensing and amplifying memory cell data in the memory cell block 200L, the S/A block 210 is connected with the bit line BL_L in one memory cell block 200L and the bit line BL_R in the other memory cell block 200R and senses and amplifies signals of the two bit lines BL_L and BL_R using the differential pair sensing. At this time, one bit line BL_L of the two bit lines BL_L and BL_R is loaded with a voltage corresponding to the memory cell data and the other bit line BL_R acts as a reference voltage line. Accordingly, in the open bit line structure, a dummy cell exists in a memory cell block at an edge. Dummy cells are memory cells that can operate normally but cannot be used. As a result the open bit line structure is more advantageous in that the size of a memory cell array is reduced but has a disadvantage of having a dummy cell that cannot be used.
FIG. 3 is a circuit diagram of a conventional cross-coupled latch S/A corresponding to the folded bit line structure illustrated in FIG. 1. Referring to FIG. 3, the S/A block 110 includes an S/A 310, isolation transistors 331L, 331R, 332L and 332R, and a precharge circuit 320.
The isolation transistors 331L, 331R, 332L and 332R are used to selectively connect the S/A block 110 with a memory cell block on one side of the S/A block 110 or a memory cell block on the other side of the S/A block 110. When a first isolation signal ISO_L is activated, first isolation transistors 331L and 332L are turned on to connect the S/A block 110 with the memory cell block on the left, so that the S/A 310 senses and amplifies data in the left memory cell block. The S/A 310 is a cross-coupled latch S/A and senses and amplifies signals of a pair of bit lines BL and /BL using the differential pair sensing. When a second isolation signal ISO_R is activated second isolation transistors 331R and 332R are turned on to connect the S/A block 110 with the memory cell block on the right, so that the S/A 310 senses and amplifies data in the right memory cell block. In other words, the S/A 310 senses signals of a pair of bit lines BL_R and /BL_R in the right memory cell block using the differential pair sensing.
As described above, in the folded bit line structure, the S/A 310 is selectively connected with the left or right memory cell block and therefore, the isolation transistors 331L, 331R, 332L and 332R are needed.
The precharge circuit 320 precharges and equalizes the pair of bit lines BL and /BL with a predetermined precharge voltage VBL in response to a precharge control signal EQ.
The S/A block 110 may further include switching elements 341 and 342 to selectively connect the bit lines BL and /BL with input/output lines IO and /IO, respectively.
FIG. 4 is a circuit diagram of a conventional cross-coupled latch S/A corresponding to the open bit line structure illustrated in FIG. 2. Referring to FIG. 4, the S/A block 210 includes the S/A 310 and the precharge circuit 320, like the S/A block 110 illustrated in FIG. 3. The S/A block 210, however does not require the isolation transistors 331L, 331R, 332L and 332R.
The S/A 310 senses and amplifies a signal of a bit line BL_L in a memory cell block on one side of the S/A block 210 and a signal of a bit line BL_R in a memory cell block on the other side of the S/A block 210 using the differential pair sensing,
As described above, the conventional cross-coupled latch S/A 310 senses and amplifies data using the differential pair sensing and requires a reference signal. The S/A 310 that senses and amplifies data through relative comparison using the reference signal is vulnerable to mismatch. Specifically, an error may occur in data sensing due to threshold voltage mismatch between transistors included in the S/A 310, transconductance mismatch between the transistors, or bit line load capacitance mismatch.
Accordingly, to overcome the problems of a dummy cell occurring in the open bit line structure and invalid data sensing occurring due to mismatch between elements in a cross-coupled latch S/A, a new bit line S/A circuit is desired.